GE Fanuc Intelligent Platforms Announces First NEBS-compliant PCI ...
Posted by ~Ray @ 2008-11-19 12:18:19
Providing further evidence of the company’s leadership in the field of communications processing. GE Fanuc Intelligent Platforms today announced the intelligent high performance. 4-port Gigabit Ethernet WANic(TM) 3850 and WANic 3860 Packet Processors. Designed for applications such as session border control secure access network address translation (NAT) traffic management and firewall the WANic 3850 and 3860 are the first packet processors to be available with NEBS (Network Equipment – Building System) compliance the most common set of safety spatial and environmental design guidelines applied to telecommunications equipment. They are also competitively advantaged by the provision of either twisted pair Small Form factor Pluggable (SFP) or short range SX fiber SFP transceivers. “Secure IP communications and multi-gigabit packet processing are growing in importance in all the markets we serve,” said Rubin Dhillon. Global Product Manager of Communications Product Management at GE Fanuc Intelligent Platforms. “The WANic 3850 and WANic 3860 uniquely combine the industry standard PCI-X form factor compliance with NEBS leading edge processing capability wire speed performance and a broad range of supporting software to enable the rapid development and deployment of secure communications solutions.” At the heart of the WANic 3850 is a Cavium OCTEON(TM) 12-core 500 MHz CN3850-SCP Secure Communications Processor while the WANic 3860 features a Cavium OCTEON 16-core 500MHz CN-3860-NSP Network Services processor enabling secure high speed connectivity and complex security processing for content-aware applications – such as the ability to examine packets at layers 2 - 7 – with wire speed performance. The processor – which delivers up to 4 Gigabits/second line speed packet processing - is complemented by up to 4 Gigabytes of high speed DDR2 packet memory. The WANic 3860 additionally features 256Mbytes of RLDRAM. A dual-issue five-stage pipeline very low latencies auto instruction pre-fetching and advanced data pre-fetching minimize memory delays and optimize application performance. High speed communications are facilitated via a PCI-SIG 1.0b-compliant 54-bit/133 MHz PCI-X bus interface. The RoHS-compliant WANic 3850 and WANic 3860 derive their flexibility from their support of multiple front panel configuration options including four front panel ports of Gigabit Ethernet supporting IEEE 1000BaseT or four front panel ports of Gigabit Ethernet supporting IEEE 1000BaseSX via SFP transceivers. A comprehensive supporting software suite – designed to improve time-to-revenue - is available including support for Debian Linux (other operating systems may also be supported) embedded boot loader and POST sample application code and a well-defined API. The software development package is optimized to simplify application integration for multi-core processor development environments. WANic 3850. 3860 offer speed security flexibility ‧ Cavium OCTEON(TM) 12-core 500MHz CN3850-SCP processor (WANic 3850) ‧ Cavium OCTEON 16-core 500MHz CN3860-NSP processor (WANic 3860) ‧ Up to 4 Gigabytes DDR2 memory ‧ Support both 1000BaseT and 1000BaseSX Gigabit Ethernet ‧ Enable complex security processing [ADVERTHERE]Related article:
http://www.asmag.com/asm/common/article_detail.aspx?c=1&module=1&id=5581
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